/**
* ===============================================================================================================
* Native driver for lan911x Ethernet Controller.
*
* There has nothing depedency on Operating System or upper layer protocol stack.
* Yeah, it just a pure and clean driver. You can build the TCP/IP stack based on this driver.
* ===============================================================================================================
* Reference
*
* https://ww1.microchip.com/downloads/en/DeviceDoc/00002266B.pdf
* https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ApplicationNotes/ApplicationNotes/en562758.pdf
*
* ===============================================================================================================
* Copyright (c) 2024, DY Young.
* All rights reserved.
*
* Licencse Term
*----------------
*
* Redistribution and use in source and binary forms, with or without modification, are permitted provided that
* the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
*    this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the
*    following disclaimer in the documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ===============================================================================================================
*/

#include "lan911x_native.h"



/** MAC CSR **/
/** ------- **/
/** accessed by MAC_CSR_CMD and MAC_CSR_DATA **/
enum mac_csr {
    MAC_CR      = 0x1,      // MAC Control
    ADDRH       = 0x2,      // MAC Address High
    ADDRL       = 0x3,      // MAC Address Low
    HASHH       = 0x4,      // Multicast Hash Table
    HASHL       = 0x5,      // Multicast Hash Table
    MII_ACC     = 0x6,      // MII Access
    MII_DATA    = 0x7,      // MII Data
    FLOW        = 0x8,      // Flow Control
    VLAN1       = 0x9,      // VLAN1 Tag
    VLAN2       = 0xA,      // VLAN2 Tag
    WUFF        = 0xB,      // Wakeup Frame Filter
    WUCSR       = 0xC,      // Wakeup Control and Status
};

/**
 * MAC_CR FORMART 5.4.1 
 * 31 : Receive all mode
 * 30-24: -
 * 23   : disable receive own
 * 22   : -
 * 21   : loopback operation mode
 * 20   : full duplex mode
 * 19   : pass all multicast
 * 18   : promiscuous mode
 * 17   : inverse filtering
 * 16   : padd bad frames
 * 15   : hash only filtering mode
 * 14   : -
 * 13   : hash/perfect filtering mode
 * 12   : late collision control
 * 11   : disable boradcast frames
 * 10   : disable retry
 * 9    : -
 * 8    : automatic pad stripping
 * 7-6  : backoff limit
 * 5    : deferral check
 * 4    : -
 * 3    : trasmitter enable
 * 2    : receiver enable
 * 1-0  : -
 */
U32_FEILD_START(vMAC_CR)
uint32 useless(0) : 2;
uint32 RXEN       : 1;
uint32 TXEN       : 1;
uint32 useless(1) : 1;
uint32 DFCHK      : 1;
uint32 BOLMT      : 2;
uint32 PADSTR     : 1;
uint32 useless(2) : 1;
uint32 DISRTY     : 1;
uint32 BCAST      : 1;
uint32 LCOLL      : 1;
uint32 HPFILT     : 1;
uint32 useless(3) : 1;
uint32 HO         : 1;
uint32 PASSBAD    : 1;
uint32 INVFILT    : 1;
uint32 PRMS       : 1;
uint32 MCPAS      : 1;
uint32 FDPX       : 1;
uint32 LOOPBK     : 1;
uint32 useless(4) : 1;
uint32 DISRCVOWN  : 1;
uint32 useless(5) : 7;
uint32 RXALL      : 1;
U32_FEILD_STOP(vMAC_CR)

/* MII_ACC Format
 * 31-16 : -
 * 15-11 : PHY Address, Inner is 0b00001
 * 10-6  : MII Reg Index (PHY reg index)
 * 5-2   : -
 * 1     : MII Write
 * 0     : MII Busy
 */
U32_FEILD_START(vMII_ACC)
#define WRITE_PHY_REG  1
#define READ_PHY_REG   0
uint32  busy         : 1;
uint32  w_nr         : 1;
uint32  useless(0)   : 4;
uint32  reg_index    : 5;
uint32  address      : 5;
uint32  useless(1)   : 16;
U32_FEILD_STOP(vMII_ACC)
